1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method of the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along in an alignment direction. Light passes through the LCD device along the long and thin shape of the liquid crystal molecules. The alignment of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment of the liquid crystal molecules is controlled to display images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer is interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one another. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field.
FIG. 1 is a view of schematically illustrating an LCD device according to the related art. In FIG. 1, the related art LCD device 11 includes transparent lower and upper substrates 10 and 30 spaced apart from and facing each other. The LCD device further includes a liquid crystal layer (not shown) interposed between the lower and upper substrates 10 and 30.
Gate and data lines 12 and 20 are formed on an inner surface of the lower substrate 10 and cross each other to define pixel regions P. Thin film transistors T are formed at crossing points of the gate and data lines 12 and 20. The thin film transistors T are arranged in a matrix type. Each thin film transistor T includes a gate electrode 14, an active layer 16, a source electrode 17 and a drain electrode 18. A pixel electrode 22 is formed at each pixel region P and is connected to a corresponding thin film transistor T. The pixel electrode 22 is formed of a transparent conductive material, which transmits light well, such as indium-tin-oxide.
A black matrix 32 is formed on an inner surface of the upper substrate 30 that faces the lower substrate 10. The black matrix 25 covers a non-display region, such as the gate lines 12, the data lines 20, and the thin film transistors T and has a lattice shape surrounding the pixel regions P. A color filter layer is formed in each opening of the lattice of the black matrix 32. The color filter layer includes red, green and blue color filter patterns 34a, 34b and 34c corresponding to the pixel regions P. A transparent common electrode 36 is formed on the black matrix 32 and the color filter layer 34a, 34b and 34c. 
The lower substrate 10 including the gate and data lines 12 and 20, the thin film transistors T and the pixel electrodes 22 may be referred to as an array substrate. The upper substrate 30 including the black matrix 32, the color filter layer 34a, 34b and 34c and the common electrode 36 may be referred to as a color filter substrate.
The array substrate and the color filter substrate are separately manufactured, aligned, and then attached with each other to thereby fabricate a liquid crystal panel. At this time, there is high possibility that light leakage occurs due to alignment margins. To prevent the light leakage, the black matrix 32 may have wider width, and it causes decrease in an aperture area.
Accordingly, to solve the problem, a color filter on array structure (COA) type LCD device has been proposed in which the color filter layer is formed on the array substrate.
FIG. 2 is a cross-sectional view of schematically illustrating an array substrate for a COA-type LCD device according to the related art.
In FIG. 2, a thin film transistor T is formed on a transparent insulating substrate 50, and the thin film transistor T includes a gate electrode 54, an active layer 58, an ohmic contact layer 60, a source electrode 62 and a drain electrode 64. In addition, a gate line 52 and a data line 66 are formed on the substrate 50. The gate electrode 54 is connected to the gate line 52, and the source electrode 60 is connected to the data line 66. Although not shown in the figure, the gate line 52 and the data line 66 cross each other to define a pixel region P. A black matrix BM and a color filter layer are formed on the substrate 50 including the thin film transistor T, the gate line 52 and the data line 66. The black matrix BM corresponds to the thin film transistor T and covers the active layer 58. The color filter layer includes red and green color filters 72a and 72b, which correspond to respective pixel regions P. The color filter layer further includes blue color filter (not shown).
A transparent pixel electrode 76 is formed on the color filter layer. The pixel electrode 76 is connected to the drain electrode 64.
Since the array substrate includes the color filter layer, it is not necessary to design by considering alignment margins. Therefore, the aperture area can be more obtained.
By the way, in an LCD device including the array substrate, an electric field is induced between the pixel electrode 76 and a common electrode (not shown), which is formed on an opposite substrate to the array substrate, and is perpendicular to the substrate 50. The LCD device has very narrow viewing angles. To increase the viewing angles of the LCD device, an in-plane switching (IPS) mode LCD device has been suggested, in which the common electrode and the pixel electrode are formed on the same substrate.
FIG. 3 is a cross-sectional view of illustrating an array substrate for a COA-IPS mode LCD device according to the related art. FIG. 4 is a schematic view of explaining dielectric constants of color filter patterns of FIG. 3.
In FIG. 3 and FIG. 4, a pixel region P is defined on an insulating substrate 80. A thin film transistor T and a color filter layer 96a, 96b and 96c, a pixel electrode 98a and a common electrode 98b are formed in the pixel region P.
The thin film transistor T includes a gate electrode 84, an active layer 88a, an ohmic contact layer 88b, a source electrode 90 and a drain electrode 92. The gate electrode 84 is connected to a gate line 82, and the source electrode 90 is connected to the data line 94. Although not shown in the figure, the gate line 82 and the data line 94 cross each other and are disposed at two sides of the pixel region P.
The color filter layer 96a, 96b and 96c is formed over the substrate 80 including the film transistor T, the gate line 82 and the data line 94. The color filter layer includes red, green and blue color filter patterns 96a, 96b and 96c. A black matrix BM is formed between the thin film transistor T and the color filter patterns 96a, 96b and 96c. 
The pixel electrode 98a and the common electrode 98b are formed over the color filter patterns 96a, 96b and 96c. The pixel electrode 98a and the common electrode 98b are spaced apart from and alternate with each other. The pixel electrode 98a is connected to the drain electrode 92 and receives signals independently in each pixel region P according to operations of the thin film transistor T. The common electrodes 98b of all the pixel regions P receive a common signal. The common signal may be a direct current (DC) voltage of about 5V.
Meanwhile, the color filter patterns 96a, 96b and 96c may be a stripe type, in which the color filter patterns 96a, 96b and 96c in vertically or horizontally adjacent pixel regions have the same color. The color filter patterns 96a, 96b and 96c may be formed by a pigment dispersion method, in which a pigment-dispersed photosensitive material is applied and then is patterned through a photolithographic process. Here, pigments are used a colored article for the color filter patterns 96a, 96b and 96c. The pigments have high lightfastness and heat resistance. The pigment dispersion method simplifies a process of forming the color filer patterns 96a, 96b and 96c. 
The green color filter pattern 96b is thicker than the red and blue color filter patterns 96a and 96c so that the color purity of the green color filter pattern 96b may be uniformalized with color purities of the red and blue color filter patterns 96a and 96c. 
However, even though the COA-IPS mode LCD device has a larger aperture ratio and wide viewing angles, hand-shaped speckles may occur due to the color filter patterns.
Referring to FIG. 4, when the pixel electrode 98a and the common electrode 98b are formed over each of the color filter patterns 96a, 96b and 96c, an electric field induced between the pixel electrode 98 and the common electrode 98b is influenced by a dielectric constant of a liquid crystal layer (not shown) in an upper side and by a dielectric constant of the color filter patterns 96a, 96b and 96c in a lower side. Accordingly, a first capacitor CLC is formed by the pixel electrode 98a, the common electrode 98b and the liquid crystal layer at each pixel region, and second capacitors CCR, CCG and CCB are formed by the pixel electrode 98a, the common electrode 98b and the color filter patterns 96a, 96b and 96c in respective pixel regions. The first capacitor CLC has the same capacitance every pixel region. The second capacitors CCR, CCG and CCB have different capacitances because the dielectric constant ∈2 of the green color filter pattern 96b is different from the dielectric constants ∈1 and ∈2 of the red and blue color filter patterns 96a and 96c. For example, the dielectric constants ∈1 and ∈2 of the red and blue color filter patterns 96a and 96c may be 4±1, and the dielectric constant ∈2 of the green color filter pattern 96b may be 5±1.
Therefore, carriers induced in the color filter patterns 96a, 96b and 96c are not smoothly refreshed. This cause afterimages or band-shaped speckles according to the color filter patterns 96a, 96b and 96c, thereby lowering image qualities.